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order this document by AN2104/d motorola, inc., 2001 AN2104 using background debug mode for the m68hc12 family by timothy j. airaudi applications engineering, microcontroller division austin, texas introduction this application note describes the basic operation of the background debug mode (bdm) and some of its applications, as it relates to motorola? m68hc12 family of microcontrollers (mcu). examples of in- circuit programming of internal flash memory and in-circuit debugging, using p&e microcomputer systems?bdm interface cable and its software, are also contained in this document. the bdm? main purpose is to allow debugging of the actual microcontroller being used in the user? target application. this takes the place of hardware such as an in-circuit emulator, which uses external components to attempt to duplicate operation of the mcu from outside of the target application. instead of having this external hardware, and a variety of potential problems, the debug logic is built into the mcu? on-chip integration module. this differs from other systems that have the debugging logic located in the central processor unit (cpu). not having the debugging logic in the cpu allows for reading and writing of memory locations, while the cpu is executing user code, with no degradation in real-time operation. this is an example of the bdm being enabled but not active. f r e e s c a l e s e m i c o n d u c t o r , i f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
application note AN2104 2 when the bdm is active, it takes over control of the microprocessor, which allows for debugging, etc. other examples of what the bdm can be used for, besides debugging, vary from programming eprom, eeprom, and flash (internal and external) to performing calibration on a target application (in manufacturing and in the field) to transferring collected and stored information to another system. theory of operation because software packages, such as p&e microcomputer systems windows development package (pkg12), take care of the operation of the bdm, this discussion does not go into great detail. for more in-depth information on this subject, refer to the documents referenced in technical resources at the end of this document. the operation of the bdm system requires a host pc with software, a bdm interface pod or bdm interface, and the user? target application. see figure 1 . the host pc is connected to the pod with a db-25 parallel cable from the pc? parallel port. the pod is then connected to the target application via a custom 6-pin bdm connector and cable. see figure 2 . figure 1. bdm system host pc interface pod bdm interface target board parallel cable cable12 from p&e microcomputer systems bdm cable 6-pin bdm connector see figure 2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
application note theory of operation AN2104 3 figure 2. bdm tool connector to communicate with the bdm on the part, two pins are used: bkgd and gnd. this method of serial interface is used to both send and receive data. a special communications protocol is used that resynchronizes at the beginning of each bit. by doing this, a greater frequency tolerance for synchronization is allowed. all bits are started with a falling edge signal that is initiated by the external host. after the mcu sees this falling edge, it waits nine e-clock cycles and then samples the level on the bkgd pin. the data is transferred msb (most significant bit) first at the rate of 16 e-clock cycles per bit. the e-clock is defined as the sysclk divided by two. the two types of bdm commands are: hardware firmware when using hardware commands, the bdm is enabled, but not active, and the user? code is running. see table 1 . these commands allow all internal and external memory, which is accessible to the microcontroller, to be read or written. this also includes on-chip i/o (input/output) and control registers. the control logic watches the bus for any free bus cycles that it can use to execute the hardware command. by using the free bus cycles, the cpu is not disturbed. if, however, a free cycle is not found within a specified time, it will use a bus cycle, which temporarily freezes the cpu. 2 4 6 5 3 1 reset bkgd v dd gnd v fp nc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
application note AN2104 4 table 1. bdm hardware commands command opcode (hex) data description background 90 none enter background mode (if ?mware enabled). read_bd_byte e4 16-bit address 16-bit data out read from memory with bdm in map (may steal cycles if external access) data for odd address on low byte, data for even address on high byte. status (1) e4 ff01, 0000 0000 (out) read_bd_byte $ff01. running user code. (bgnd instruction is not allowed.) ff01, 1000 0000 (out) read_bd_byte $ff01. bgnd instruction is allowed. ff01, 1100 0000 (out) read_bd_byte $ff01. background mode active (waiting for single wire serial command). read_bd_word ec 16-bit address 16-bit data out read from memory with bdm in map (may steal cycles if external access) must be aligned access. read_byte e0 16-bit address 16-bit data out read from memory with bdm out of map (may steal cycles if external access) data for odd address on low byte, data for even address on high byte. read_word e8 16-bit address 16-bit data out read from memory with bdm out of map (may steal cycles if external access) must be aligned access. write_bd_byte c4 16-bit address 16-bit data in write to memory with bdm in map (may steal cycles if external access) data for odd address on low byte, data for even address on high byte. enable_ firmware (2) c4 ff01, 1xxx xxxx (in) write byte $ff01, set the enbdm bit. this allows execution of commands which are implemented in ?mware. typically, read status, or in the msb, write the result back to status. write_bd_word cc 16-bit address 16-bit data in write to memory with bdm in map (may steal cycles if external access) must be aligned access. write_byte c0 16-bit address 16-bit data in write to memory with bdm out of map (may steal cycles if external access) data for odd address on low byte, data for even address on high byte. write_word c8 16-bit address 16-bit data in write to memory with bdm out of map (may steal cycles if external access) must be aligned access. 1. status command is a specific case of the read_bd_byte command. 2. enable_firmare is a specific case of the write_bd_byte command. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
application note theory of operation AN2104 5 to execute firmware commands, the user must have the bdm enabled and active. see table 2 . when the bdm is active, it has control of the cpu, which executes code out of the bdm rom. table 2. bdm firmware commands command opcode (hex) data description read_next 62 16-bit data out x = x + 2; read next word pointed to by x read_pc 63 16-bit data out read program counter read_d 64 16-bit data out read d accumulator read_x 65 16-bit data out read x index register read_y 66 16-bit data out read y index register read_sp 67 16-bit data out read stack pointer write_next 42 16-bit data in x = x + 2; write next word pointed to by x write_pc 43 16-bit data in write program counter write_d 44 16-bit data in write d accumulator write_x 45 16-bit data in write x index register write_y 46 16-bit data in write y index register write_sp 47 16-bit data in write stack pointer go 08 none go to user program trace1 10 none execute one user instruction then return to bdm taggo 18 none enable tagging and go to user program f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
application note AN2104 6 bdm registers seven bdm registers are mapped into addresses $ff00?ff06. see table 3 . note: remember that the bdm firmware rom and registers contain different data than the normal memory mapped locations for these addresses. only two registers are discussed here: bdm status register (status) bdm ccr (condition code register) holding register (ccrsav) the bdm status register can be read at any time, but must not be written to during bdm operation. see figure 3 for a description of the bits. this register can be read or written by bdm commands or firmware. enbdm ?enable bdm bit (permit active background debug mode) 0 = bdm cannot be made active (hardware commands still allowed). 1 = bdm can be made active to allow firmware commands. table 3. bdm registers address register mnemonic $ff00 bdm instruction register instruction $ff01 bdm status register status $ff02?ff03 bdm shift register shifter $ff04?ff05 bdm address register address $ff06 bdm ccr holding register ccrsav address: $ff01 bit 7 654321 bit 0 read: enbdm edmact entag sdv trace 0 0 0 write: reset: 00000000 single-chip peripheral: 10000000 figure 3. bdm status register (status) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
application note theory of operation AN2104 7 bdmact ?background mode active status bit 0 = bdm not active 1 = bdm active and waiting for serial commands entag ?instruction tagging enable bit set by the taggo instruction and cleared when bdm is entered 0 = tagging not enabled or bdm active 1 = tagging active (bdm cannot process serial commands while tagging is active.) sdv ?shifter data valid bit shows that valid data is in the serial interface shift register. used by firmware-based instructions. 0 = no valid data 1 = valid data trace asserted by the trace1 instruction the second register of interest is the bdm ccr holding register. this register contains the value of the cpu? condition code register (ccr) from the user? program upon entering the bdm. see figure 4 . operation of active bdm here is a brief description of what transpires when going into the active bdm: when the cpu gets the command to go into the bdm, the user? return address is stored in a temporary register. next, the bdm rom is turned on and the cpu fetches a vector that points to the beginning of the bdm firmware program. address: $ff06 bit 7 654321 bit 0 read: ccr7 ccr6 ccr5 ccr4 ccr3 ccr2 ccr1 ccr0 write: reset: 00000000 figure 4. bdm ccr holding register (ccrsav) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
application note AN2104 8 next the bdm firmware saves the contents of the user? d register in another temporary register and then saves the user? ccr register in the ccrsav register. the bdm firmware then checks the enbdm bit in the status register to see if it will be allowed to go into the active bdm. if it is, the bdm firmware enters a software loop and waits for a valid firmware command in which to execute. the user? program counter (pc), stack pointer (sp), and x and y registers are not changed by the bdm firmware, so the user doesn? need to save or stack these values. during exit from the bdm, the user? register values are restored and a value is stored in the bdm status register. then a jump command is executed to resume execution of the user? program. m68hc12 operating modes the two basic modes of operation (see table 4 ) for the m68hc12 family are: normal modes ?provide protection for control registers from being accidentally modified special modes ?allow access to these control registers for system development and special testing if any of the normal operating modes are entered (bkgd high), the bdm is available, but must be enabled and/or made active. if the special single-chip mode is selected (bkgd, moda, and modb all low), the bdm comes up enabled and active. table 4 also shows that the states of the bkgd, moda, and modb pins determine a specific mode where the port a and port b pins are configured for different functions. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
application note m68hc12 operating modes AN2104 9 these examples deal with the levels on the bkgd, moda, and modb pins during a reset to determine which mode the part will come up in. the user can also change the mode of operation by writing to the mode register after the part is powered up. see figure 5 . the mode register can be read at any time. however, writing to this register presents some restrictions. first, if the part comes up in the normal mode, it can be changed only to another normal mode. this change can be done only once. the special mode does not have this limitation, since the values of the moda and modb pins can be changed as many times as desired as long as the part remains in special mode. next, coming up in the special mode, the part can change to the normal mode, but must write to the smodn bit in this register two times, as the first write is ignored. table 4. mode selection bkgd modb moda mode port a port b 0 0 0 special single chip general- purpose i/o general- purpose i/o 0 0 1 special expanded narrow addr[15:8] data[7:0] addr[7:0] 0 1 0 special peripheral addr data addr data 0 1 1 special expanded wide addr data addr data 1 0 0 normal single chip general- purpose i/o general- purpose i/o 1 0 1 normal expanded narrow addr[15:8] data[7:0] addr[7:0] 110 reserved (forced to peripheral) 1 1 1 normal expanded wide addr data addr data f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
application note AN2104 10 operating mode and background debug mode hints these hints will help steer the user away from the most commonly made mistakes. the states of the moda and modb pins, upon power-up, determine how the port a and port b pins will be configured (see table 4 ). the bkgd pin is used for two purposes: it determines, upon reset, which operating mode the part will enter, normal or special (see table 4 ). then it is used as the serial communication pin for the bdm. once the part is operating in a mode, the mode can be changed by writing to the mode register. the limitations to this are listed in figure 5 . when in normal operating mode, special modes cannot be accessed. address: $000b bit 7 6 5 4321 bit 0 read: smodn modb moda estr ivis ebswai 0 eme write: reset states: normal expanded narrow: 1 0 1 10000 normal expanded wide: 1 1 1 10000 special expanded narrow: 0 0 1 11001 special expanded wide: 0 1 1 11001 peripheral: 0 1 0 11001 normal single-chip: 1 0 0 10000 special single-chip: 0 0 0 11001 figure 5. mode register (mode) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
application note background debug mode application examples AN2104 11 when in normal operating mode, another normal operating mode can be accessed, but this can be done only once. to change to the normal operating mode, when the part is in special operating mode, a 1 (one) must be written twice to the smodn bit in the mode register. when the part comes up in special single-chip mode, the bdm is enabled and active. when the part comes up in special single-chip mode, it accesses the bdm rom, not the normal memory mapped locations at $ff00?ffff. to perform hardware commands, the bdm does not need to be active (see table 1 ). to perform firmware commands, the bdm must be enabled and active (see table 2 ). the bdm does not operate in stop mode. background debug mode application examples two bdm application examples are given here in a step-by-step format. in-circuit programming of internal flash this application example of the bdm explains how to perform in-circuit programming of the internal flash memory of an mc68hc912b32 using p&e microcomputer systems?cable12 pod and software (see figure 1 ). the target board for this example is the m68evb912b32 evaluation board. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
application note AN2104 12 follow these steps in order: 1. load p&e? pkg12z software. 2. connect a parallel cable from the host pc to the cable12 pod. 3. connect the 6-pin bdm cable from the pod to the evaluation board making sure that pin 1 of the cable is connected to pin 1 of the pod and target. on the evaluation board, make sure that jumpers w3 and w4 are in the evb positions and jumper w7 is in the v dd position. 4. apply +5 vdc to p5 of the evaluation board and +12 vdc to w8. 5. launch p&e? winide. 6. open p&e? sample code named sci. 7. assemble/compile this file. see figure 6 . 8. launch the programmer. if the correction assistant window opens, select the correct parallel port being used. defaults should work for the other options in this window. see figure 7 . 9. select the 9b32_32k.12p programming algorithm. 10. input $8000 for the base address when prompted. 11. move jumper w7, on the evaluation board, to the v pp position. 12. select erase module . 13. ensure that the sci.s19 file is in the s-record in the configuration window. if not, select specify s record and select this file. 14. select program module . 15. after programming is complete, move jumper w7 to the v dd position. do not leave the programming voltage on the flash. 16. the sci.s19 file has now been erased and programmed into the flash of the mc68hc912b32 using the bdm. select verify module to verify that this programming is correct. the code also can be viewed by selecting show module at address $8000. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
application note background debug mode application examples AN2104 13 figure 6. p&e? winide window f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
application note AN2104 14 figure 7. p&e? programmer window in-circuit debugging this application example of the bdm explains how to perform in-circuit debugging of an mc68hc912b32 using p&e microcomputer systems cable12 pod and software (see figure 1 ). the target board for this example will be the m68evb912b32 evaluation board. follow these steps in order: 1. load p&e? pkg12z software. 2. connect a parallel cable from the host pc to the cable12 pod. 3. connect the 6-pin bdm cable from the pod to the evaluation board making sure that pin 1 of the cable is connected to pin 1 of the pod and target. on the evaluation board, make sure that f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
application note background debug mode application examples AN2104 15 jumpers w3 and w4 are in the evb positions and jumper w7 is in the v dd position. 4. apply +5 vdc to p5 of the evaluation board. 5. launch p&e? winide. 6. open p&e? sample code named sci. 7. assemble/compile this file. see figure 6 . at this point, ensure that the flash is programmed as in the previous application example in in-circuit programming of internal flash . 8. launch the debugger. if the correction assistant window opens, select the correct parallel port being used. defaults should work for the other options in this window. see figure 8 . 9. verify that the correct s19 is loaded in the debugger by selecting the file drop down menu and selecting load s19 file and the sci.s19 file. 10. in the execute drop down menu, select reset processor . 11. from this point, the code can be debugged by selecting single step , multiple step , or go . breakpoints also can be set by selecting the line of code chosen for a breakpoint, clicking the right mouse button, and selecting toggle breakpoint at cursor. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
application note AN2104 16 figure 8. p&e? debugger window summary this application note gives an overview of the bdm as it relates to motorola? m68hc12 family of mcus. by providing the appropriate connections for the bdm in the user? application, and using a bdm interface pod with software, it is easy to debug code, erase, or program the flash in the target application. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
application note technical resources AN2104 17 technical resources software and hardware engineering: motorola m68hc12 by fredrick m. and james m. sibigtroth cpu12 reference manual , document order number cpu12rm/ad m68hc12b family advance information , motorola document order number m68hc12b/d mc68hc812a4 advance information , motorola document order number mc68hc812a4/d mc68hc912d60 advance information , motorola document order number mc68hc912d60/d mc68hc912dg128 advance information , motorola document order number mc68hc912dg128/d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
application note AN2104 18 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
application note technical resources AN2104 19 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required application note f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .

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